Hardware description languages, such as VHDL (Very High Speed Integrated Circuit Hardware Description Language), are widely used for the design, documentation, and simulation of integrated electronic circuitry. The 1993 version of VHDL is described in IEEE Standard VHDL Language Reference Manual, IEEE Std. 1076-1993. VHDL offers three different modes for the characterization of a complex integrated circuit: structural, data flow, and behavioral descriptions. The VHDL structural description mode focuses on the arrangement of interconnected hardware components, or "blocks," defined by type and interface. The VHDL data flow description mode breaks down the circuit design into a set of register assignments that take place under the control of specified gating ports. The VHDL behavioral description mode defines the design in terms of a series of sequential modules that resemble a high-level programming language. A design can be characterized by a collection of structural, data flow, and behavioral descriptions.
In the VHDL structural description mode, the designer codes various component declarations that provide generic definitions of different hardware components such as multiplexers, latches, and shift registers. Once declared, a component can be instantiated as desired to define particular component instances, or "modules," that form part of the overall integrated circuit design. A component declaration includes a component port list that defines the generic interface to the component, i.e., the input and output ports. A module declaration similarly includes a module port list, but specifies one or more particular signals to be connected to the port interface. Thus, a module, representing an instance of the component, assigns particular signals to the generic port list. In this manner, the module is interconnected with other modules in the overall design.
The human designer generally is required to manually enter the component port lists and module port lists. Unfortunately, the modules and associated port lists within a given design can be difficult to generate and maintain. As a design evolves, for example, the content of the port lists is subject to constant change. Moreover, the changes occur within an extremely complex design having potentially hundreds of modules and port lists that interact with one another. Consequently, maintenance of the module port lists presents a significant challenge.
If a port list is incorrect, the overall design or portions thereof may fail to simulate correctly. In particular, when the module port list omits one or more of the necessary ports, the associated module will not operate properly. Also, the port list error can propagate downstream to other modules that interface with the suspect module. Thus, lack of port list integrity compromises the function of the overall design and causes incorrect simulation.
Identification of the source of the problem, i.e., a defective port list, is a painstaking manual process that can take hours and, in many cases, days. This manual debugging effort can result in substantial delays and drains resources from the design effort, significantly increasing the design cycle and time to market. In the end, port list debugging is a costly nuisance that is difficult to avoid due to design complexity and the prevalence of human error.